1. Field of the Invention
The present invention relates to network technology and more particularly, to a network signal processing circuit assembly, which uses signal coupling capacitors for causing a back-EMF (back-electro motive force) to increase the voltage difference, ensuring signal integrality and reliability, avoiding signal distortion and saving power loss.
2. Description of the Related Art
Following fast development of computer technology, desk computers and notebook computers are well developed and widely used in different fields for different applications. It is the market trend to provide computers having high operating speed and small size. Further, network communication technology brings people closer, helping people to gather information about living, learning, working and recreational activities. By means of network communication, people can communicate with one another to send real time information, advertising propaganda or e-mail. Further, through the Internet, people can search information, send instant messages, or play on-line video games. The development of computer technology makes the relationship between people and network unshakable and inseparable.
Connecting a computer or electronic apparatus to a network for data transmission can be done by a cable connection technique or a wireless transmission protocol. A cable connection technique needs the installation of a network connector. Further, following the development of network application technology, network data transmission capacity has been greatly increased. To satisfy the demand for high data transmission capacity, network transmission speed has been greatly improved from the early 10 Mbps to 100 Mbps or 1 Gbps. Nowadays, fiber-optic network transmission speed can be as high as 10 Gbps and up. When under the network transmission speed of 10 Mbps, Manchester coding is adopted. Because the waveform of the signal being transmitted through the cable at 10 Mbps is symmetric (see FIG. 7), in case of signal distortion or signal error, signal compensation can be performed using this symmetric characteristic, obtaining integral and accurate signal data. When under the network transmission speed of 100 Mbps, 3-level ternary code is used. This 3-level ternary code is to cut out bitstream into 8-bit bytes, enabling each 8-bit byte to be converted into a respective 6-symbol codeword. Thus, the required clock frequency can be reduced from 33.3 MHz to 25 MHz without surpassing the tolerable limit of 30 MHz of a double twisted cable.
However, when under the network transmission speed of 1 Gbps, the clock frequency is 125 MHz, and the 4D-PAM5 code is used. According to this 4D-PAM5 code, each level represents a symbol, and each symbol represents a 2-bits data. Thus, signal can be greatly compressed to enhance the transmission speed. However, the waveform of this signal is asymmetric (see FIG. 8). In order to prevent distortion or failure due to removal of network signal (the part of negative voltage), a bias must be provided, enabling signal to be smoothly transmitted in the positive voltage.
A conventional network connector has built therein transformer modules and common-mode suppression modules. As shown in FIG. 9, a conventional network connector comprises a circuit board A, and multiple transformer coils B and filter coils C installed in the circuit board A. The transformer coils B and the filter coils C each comprise a wire core D, and a lead wire D1 wound round the wire core D with the ends thereof bonded to respective contacts at the circuit board A. Because the winding of the transformer coils B and the filter coils C cannot be achieved by an automatic machine and must be done by labor, the fabrication efficiency of this kind of network connector is low. Further, the lead wire may be broken easily during winding, thereby increasing the cost. Further, fabrication by labor cannot accurately control the coil winding tightness and number of turns, affecting product quality stability.
Further, Taiwan Patent Application 101207955, or the Patent Number M436860 published on Patent Gazette on Sep. 1, 2012, issued to the present inventor, discloses a network signal processing circuit. According to this design, as shown in FIG. 10, the network signal processing circuit, referenced by E, has its two opposite ends respectively electrically connected to a network connector E1 and a network-on-chip E2. The network signal processing circuit E comprises a plurality of channels E3, a plurality of signal coupling capacitors E4 respectively coupled to the channels E3, and a plurality of inductors E5 electrically connected in series to the signal coupling capacitors E4. The inductors E5 are electrically connected to a bias providing terminal E51, a voltage stabilizing capacitor E52 and a grounding terminal E53. The bias providing terminal E51 provides a DC voltage level through the inductors E5 to the channels E3, keeping the signals being transmitted through the channels E3 within the positive voltage range. Therefore, signals being transmitted through the channels E3 will not be cut off, avoiding distortion and ensuring signal integrality. Further, the inductors E5 has the characteristics of being in an open circuit to DC voltage and close circuit to AC high-frequency signal. When the bias providing terminal E51 provides a DC voltage level to the inductors E5, the inductance value will be lowered for enabling the bias voltage to pass, isolating the high-frequency network signal, and therefore voltage signal can simply be transmitted through the channels E3 and will not be shunted to the ground. Further, the voltage stabilizing capacitor E52 and the grounding terminal E53 can balance the voltage value of the channels E3. However, voltage stabilizing capacitor E52 and the grounding terminal E53 will also cause the power supply provided by the bias providing terminal E51 to be grounded, causing a significant power loss.
Therefore, there is a strong demand for a network signal processing circuit assembly, which eliminates the drawbacks of the aforesaid prior art designs.